Scan chains are a technique used in
Design For Test. The objective is to make testing easier by providing a simple way to set and observe every
flip-flop in an
IC. A special signal called scan enable is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long
shift register, one input pin provides the data to this chain, and one output pin is connected to the output of the chain. Then using the chip's
clock signal, an arbitrary pattern can be entered into the chain of flips flops, and/or the state of every flip flop can be read out.
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<
electronics> (Or "Scan-In, Scan-Out") A electronic circuit design technique which aims to increase the controllability and observability of a digital
logic circuit by incorporating special "
scan registers" into the circuit so that they form a
scan path.
Some of the more common types of scan design include the
multiplexed register designs and
level-sensitive scan design (LSSD) used extensively by
IBM.
Boundary scan can be used alone or in combination with either of the above techniques.
["Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman, ISBN 0-7167-8179-4].
["Design of Testable Logic Circuits" by R.G. Bennetts, (Brunel/Southhampton Universities), ISBN 0-201-14403-4].
(1995-02-23)
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