Standard Cell

:For the battery used as a voltage reference, see Weston cell. In semiconductor design, standard cell methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level VLSI-layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class that standard-cell belongs to) makes it possible for one designer to focus on the high-level (logical function) aspect of digital-design, while another designer focused on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC).
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Noun
1. a primary cell used as a standard of electro-motive force
(hypernym) voltaic cell, galvanic cell, primary cell
(hyponym) Clark cell, Clark standard cell

an integrated circuit design where circuit blocks from previous designs are combined to create a new design.