Reduced instruction set computer

The reduced instruction set computer (RISC, pronounced like "risk") is a CPU design philosophy that favors an instruction set reduced both in size and complexity of addressing modes, in order to enable easier implementation, greater instruction level parallelism, and more efficient compilers.  As of 2007, common RISC microprocessors families include the DEC Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture (including PowerPC), and SPARC. The idea was originally inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. Additionally, the performance gap between the processor and main memory was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses.
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Le microprocesseur à jeu d'instruction réduit ou reduced instruction-set computer en anglais est une architecture matérielle de microprocesseurs. On l'a opposé à la fin des années 1980 et au début des années 1990 à l'architecture CISC (complex instruction-set computer). La sortie d'architectures hybrides comme le Pentium (CISC émulé par du RISC) a mis fin, par disparition de repères, à cette guerre qui était devenue bien plus marketing que technique vers 1990, les techniques ayant évolué de part et d'autre et chacune comparant ses procédés à ceux de l'autre... six ans plus tôt.
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Reduced Instruction Set Computing (RISC), zu deutsch Rechnen mit reduziertem Befehlssatz, ist eine bestimmte Designphilosophie für Prozessoren.
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RISC (Reduced Instruction Set Computers) - nazwa architektury mikroprocesorów która została przedstawiona pod koniec lat 70. w teoretycznych pracach na uniwersytecie Berkeley oraz w wynikach badań Johna Cocke z Thomas J. Watson Research Center.Ówczesne procesory (budowane w architekturze CISC) charakteryzowały się bardzo rozbudowaną listą rozkazów, ale jak wykazały badania tylko nieliczna ich część była wykorzystywane w statystycznym programie. Okazało się np. że ponad 50% rozkazów w kodzie to zwykłe przypisania (zapis zawartości rejestru do pamięci i odwrotnie).
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RISC, acronimo dell'inglese  Reduced Instruction Set Computer, indica una filosofia di progettazione di architetture per microprocessori formate da un set di istruzioni contenente istruzioni in grado di eseguire operazioni semplici che possono essere eseguite in tempi simili. Questa filosofia di progettazione è opposta a quella alla base delle architetture complex instruction set computer che invece predilige processori dotati di istruzioni anche molto complesse con tempi di esecuzione molto diversi a seconda delle istruzioni. I più comuni processori RISC sono:AVR, PIC, ARM, DEC Alpha, PA-RISC, SPARC, MIPS e POWER.
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