Planar Process

The Planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. The process was developed by Jean Hoerni, one of the Traitorous Eight, while working at Fairchild Semiconductor.The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p-n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
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an IC made in such a way that all of the PN junctions intersect the top surface of the semiconductor. In planar processing photolithography and etching create openings in films on the surface of the wafer and the opening define diffused and or implanted junctions formed into the wafer.