Pipelining redirects here. For HTTP pipelining, see
HTTP pipelining. An instruction pipeline is a technique used in the design of
computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time). Pipelining assumes that successive instructions in a program sequence will overlap in execution, as suggested in the next diagram (vertical 'i' instructions, horizontal 't' time). Most modern CPUs are driven by a clock. The CPU consists internally of logic and
flip flops. When the clock arrives, the flip flops take their new value and the logic then requires a period of time to decode the new values. Then the next clock pulse arrives and the flip flops again take their new values, and so on. By breaking the logic into smaller pieces and inserting flip flops between the pieces of logic, the delay before the logic gives valid outputs is reduced. In this way clock period can be reduced. For example, the RISC pipeline is broken into five stages with a set of flip flops between each stage.Instruction fetch Instruction decode and register fetch Execute Memory access Register write back
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