Branch Target Buffer

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Branch target predictor
In computer architecture, a branch target predictor is the part of a processor that predicts the target of a conditional branch or unconditional jump instruction before that instruction has been fetched from the instruction cache. The instruction cache is a specialized kind of CPU cache.Branch target prediction is not the same as branch prediction. Branch prediction attempts to guess whether the branch will be taken or not. Branch target prediction attempts to guess the target of the branch or unconditional jump before it is computed from parsing the instruction itself.In more parallel processor designs, as the instruction cache latency grows longer and the fetch width grows wider, branch target extraction becomes a bottleneck. The recurrence is:Instruction cache fetches block of instructionsInstructions in block are scanned to identify branchesFirst predicted taken branch is identifiedTarget of that branch is computedInstruction fetch restarts at branch target
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Branch Target Buffer
<processor> (BTB) A register used to store the predicted destination of a branch in a processor using branch prediction?
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(1995-05-05)


(c) Copyright 1993 by Denis Howe

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